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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:12:22 10/05/2013 
-- Design Name: 
-- Module Name:    comparator_32 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity comparator_32 is
    Port ( op1 : in  STD_LOGIC_VECTOR (31 downto 0);
           op2 : in  STD_LOGIC_VECTOR (31 downto 0);
           op1IsLess, isEqual : out STD_LOGIC);
end comparator_32;

architecture Behavioral of comparator_32 is

begin
	op1IsLess <= 	'1' when signed(op1) < signed(op2) else
						'0';
	isEqual <= 	'1' when op1 = op2 else
					'0';
end Behavioral;

